Low-voltage, low-area, nW-power CMOS digital-based biosignal amplifier

This paper presents the operation principle and the silicon characterization of a power efficient ultra-low voltage and ultra-low area fully-differential, digital-based Operational Transconductance Amplifier (OTA), suitable for microscale biosensing applications (BioDIGOTA). Measured results in 180nm CMOS prototypes show that the proposed BioDIGOTA is able to work with a supply voltage down to 400 mV, consuming only 95 nW. Owing to its intrinsically highly-digital feature, the BioDIGOTA layout occupies only 0.022 mm2 of total silicon area, lowering the area by 3.22× times compared to the current state of the art, while keeping reasonable system performance, such as 7.6 NEF with 1.25 μVRMS input referred noise over a 10 Hz bandwidth, 1.8% of THD, 62 dB of CMRR and 55 dB of PSRR

Low temperature sensitivity CMOS transconductor based on GZTC MOSFET condition

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/ºC

MOSFET ZTC condition analysis for a self-biased current reference design

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V

Mismatch model for MOS transistors

Diversos modelos teóricos para o descasamento entre dispositivos na tecnologia MOS foram propostos desde a década de ’80, sendo que geralmente estes pecam ou pela simplicidade, sendo válidos apenas sob condições de operação específicas, ou por resultarem em expressões muito complexas, o que torna necessário o uso de pesados recursos computacionais. Esta tese propõe uma abordagem inovadora para a modelagem do descasamento dos transistores de efeito de campo de porta isolada (MOSFETs), chegando a resultados melhores e mais abrangentes que outras propostas já publicadas. Para tanto, as variações microscópicas na corrente que flui pelo dispositivo, resultado das flutuações na concentração de dopantes na região ativa, são contabilizadas levando-se em conta a natureza não-linear do transistor. O resultado é um modelo compacto que prevê o descasamento com grande exatidão e de forma contínua, em todas as condições de operação do transistor, da inversão fraca à forte, e da região linear à saturação, necessitando apenas dois parâmetros de ajuste. Duas versões de circuitos de teste foram desenvolvidas e implementadas em diversas tecnologias, como forma de se obter suporte experimental para o modelo. A versão mais avançada possibilita a caracterização elétrica, de forma totalmente automática, de um grande número de dispositivos. O uso deste modelo substitui com vantagens a tradicional simulação Monte Carlo, que exige grandes recursos computacionais e consome muito tempo, além de oferecer uma excelente ferramenta de projeto manual, como é demonstrado através do desenvolvimento de um conversor digitalanalógico, cujo resultado experimental corroborou a metodologia empregada.Many mismatch models were proposed for the MOS devices since the ‘80s, but they use either too simple approaches, being restricted to specific operating conditions, or too complex expressions, only useful through hard computational resources. This thesis proposes a new approach for MOSFETs mismatch modeling, presenting better and more general results than that found in preceding articles. In this approach, the microscopic variations of the drain current, caused by random doping fluctuation inside the channel region, are integrated along the channel, considering the main transistor nonlinearities. It results in a compact model that accurately predicts mismatch, continuously over any transistor operating condition, from weak to strong inversion, and from linear to saturation region, and only needing two fitting parameters. Two versions of a test chip were developed and fabricated in many technologies to give experimental support to this model. The most advanced of them makes the automated electrical characterization possible for a huge number of devices. This model can surpass the traditional Monte Carlo simulation method with advantages, and can also be used as a hand-design tool, as demonstrated here through the design of a digital-to-analog converter

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 m technology confirm the accuracy of our mismatch model under various bias conditions

A compact model of MOSFET mismatch for circuit design

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 m technology confirm the accuracy of our mismatch model under various bias conditions

Dynamic and static calibration of ultra-low-voltage, digital-based operational transconductance amplifiers

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed